By Dirk Stroobandt
The roots of this booklet, and of the hot examine box that it defines, lie within the scaling of VLSI expertise. With gigahertz procedure clocks and ever accelerating layout and procedure suggestions, interconnects became the restricting issue for either functionality and density. This expanding impression of interconnects at the procedure implementation house necessitates new instruments and analytic thoughts to help the method dressmaker. With admire to modeling and research, the reaction to interconnect dom inance is evolutionary. Atomistic- and grain-level types of interconnect constitution, and function types at multi-gigahertz working frequencies, jointly consultant the choice of stronger fabrics and approach applied sciences (e. g. , damascene copper wires, low-permittivity dielectrics). formerly in major results (e. g. , mutual inductance) are extra into functionality mod els, as older approximations (e. g. , lumped-capacitance gate load versions) are discarded. although, on the system-level and chip making plans point, the required reaction to interconnect dominance is innovative. Convergent layout flows don't require in basic terms dispensed RLC line versions, repeater knowledge, unifi cations with extraction and research, and so on. fairly, concerns equivalent to wiring layer project, and early prediction of the source and function envelope for the method interconnect (in specific, in keeping with statistical versions of the procedure interconnect structure), additionally develop into serious. certainly, system-level interconnect prediction has emerged because the enabler of more advantageous interconnect modeling, less expensive procedure architectures, and extra effective layout technology.
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Additional info for A Priori Wire Length Estimates for Digital Design
I return to this issue extensively in chapter 3. 4. 2. Schematic model for the physical architecture. MODEL FOR THE ARCIDTECTURE In the previous section we discussed the circuit model. However, the length of a circuit interconnection only gets its meaning after the placement of the circuit in a physical architecture.
Wiring area is mainly dictated by the total length of nets, rather than by the length of individual source-sink pairs (for point-to-point connections both are, of course, equal). In chapter 3, a model for multi-terminal nets is presented that allows us to estimate lengths of multi-terminal nets. Also the routing of wires mainly depends on the total net length. Wire length estimations of entire nets are therefore denoted as length estimates for routing-related applications. 3NMOS denotes the n-channel MOS ("Metal Oxide Semiconductor').
In order to compare different circuits to each other. we must be able to characterize them. The characterization parameters that can be immediately obtained from the netIist are the number of components in the circuit, the number of nets, the distribution of the terminals over the components, and the distribution of the terminals over the nets (the net degree). Apart from the immediately 'measurable' characteristic parameters, there are other parameters that can characterize circuits. The most important one is the interconnection topology.